Heterogeneous Quantum Architectures Significantly Reduce Qubit Requirements for Fault-Tolerant Computing
This paper introduces a heterogeneous quantum computing architecture that integrates task-specific hardware selection, quantum error correction (QEC) encoding, and a comprehensive microarchitecture for fault-tolerant interfaces. By unifying physical device challenges with QEC-code-driven considerations, the approach achieves substantial reductions in physical qubit overhead and algorithmic logical error rates. The proposed architecture and accompanying compiler demonstrate significant resource optimization for complex quantum algorithms, including factoring.